Samsung Electronics has announced 3 nm gate-all-around (GAA) process called 3GAE

From FinFET to GAA: Samsung Electronics’s fab journey to 3nm and 2nm

Samsung Electronics has announced that its development of the 3 nm gate-all-around (GAA) process called 3GAE is on track and that it has made available version 0.1 of its process design kit (PDK) in April this year. Samsung is adopting the GAA architecture for 3-nm process nodes to overcome the physical scaling and performance limitations of the FinFET architecture.

Samsung’s fab executives are quick to point out that the conventional GAA based on nanowire—also known as GAAFET—requires a larger number of stacks due to its small effective channel width. On the other hand, Samsung’s multi-bridge-channel FET (MBCFET) technology uses a nanosheet architecture to enhance gate control. That, in turn, enables greater current per stack.

Another key distinction: the existing FinFET structures must discretely modulate the number of fins. Here, MBCFET provides greater design flexibility by controlling the nanosheet width. Samsung claims that its first 3-nm GAA process node utilizing MBCFET will allow up to 35% decrease in area, 30% higher performance, and 50% lower power consumption than the 5-nm process. Moreover, the logic yield of 3 nm is approaching a level similar to the 4-nm process, which is currently in mass production.